LPCR: Information-Theory-Based Low-Power Code Reordering for Serial Links in Network-on-Chip
Morteza Adelkhani, Ali Suvizi, Farzaneh Arzaghi, Sara Zamani, Mohammad Salehi, Muhammad Shafique · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
Manycore platforms have emerged as a promising candidate to meet the increasing computation demand in high-performance computing (HPC). Networks-on-Chip (NoC) have proposed appropriate on-chip communication solutions for manycore platforms. However, the increase in the number of cores and the size of cache in a single chip raises the power dissipation of NoC, potentially impacting data communication performance. The primary source of power dissipation in NoC is the switching activity of data bits transmitted through data links. In this study, we introduce an analytical method, based on information theory, to assess data representation or coding methods from the perspectives of the switching activity of data bits and the length of codewords used for data symbols. Subsequently, we propose a lightweight yet efficient Low-Power Code Reordering (LPCR) technique, that can be integrated into existing coding methods to decrease power consumption. The comprehensive evaluations presented in this paper demonstrate that our LPCR method, reduces link power consumption through reducing the switching activity of data bits up to 13.2%, on average 8.8%, while increases the number of data bits by less than 4.9%, this decreases link energy consumption by 9.9% when applied to the coding methods which aim to minimize the number of data bits (e.g., Huffman coding). However, LPCR does not change the number of data bits when implemented on the Binary coding and, decreases the number of bits up to 12% when implemented on the Most Frequent Least Power (MFLP) method. LPCR impose a very low time and memory overhead at runtime. It needs a data array ranging from 256B for Binary to 32KB for MFLP methods and executes one extra command to read codewords from the array.