Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation
Haoyuan Wang, Thomas Nijssen, Scott Beamer · 2024
Designing a digital integrated circuit requires many register transfer level (RTL) simulations for design, debugging, and especially verification. To cope with the slow speed of RTL simulation, industry frequently uses private server farms to run many simulations in parallel. Surprisingly, the implications of parallel runs of different RTL simulations have not been extensively explored. Moreover, in modern digital hardware, there is a growing trend to replicate components to scale out. However, the potential for circuit deduplication has been mostly overlooked.