ANALYSING THE PERFORMANCE TRADEOFFS OF PARAMETERIZED VLSI ARCHITECTURE USING TREE-LOGIC MACHINE LEARNING SYSTEM
T. Gobinath, A Sumalatha, M. Vinoth Kumar, Dharani M · ICTACT Journal on Microelectronics · 2023
This paper deals with the design of a tree logic machine learning system agent that is based on a hybrid technique that blends graph handmade properties with graph neural network embeddings. It is a combination of traditional reinforcement learning and deep learning that involves the substitution of tree logic machine learning system in the learning process. The proposed agent uses a new EMAC-TLML system that is compatible with the inference made by deep learning networks that use 8 bits of precision, and we demonstrate that this compatibility works quite well. It has been demonstrated that the proposed research uses resources and produces energy delay products in a manner that is analogous to that of their floating-point counterparts. The solution that has been suggested provides a greater maximum working frequency in contrast to the floating-point method.