Improving the 8T SRAM Cell Design for Fault Tolerance and Power Efficiency
Ajay Sudhir Bale, S. Saranya, T S Arulananth, Varun Yogi Shanthakumar, T Y Satheesha, Gururaj Murtugudde · 2024
We have designed an 8T SRAM model in this work where we have worked on the issues of read/write efficiency, leakage current and also fault tolerance. The design used in this work consists of 8 transistors, 2 PMOS and 6 NMOS. Here the two transistors make a 2-NOT gate structure. The objective of this work is to design a SRAM which can work in challenging conditions very efficiently. This work has concentrated on lowering the value of leakage current, which is key in read/write operations. The design shows promising results for the above-mentioned issues. We have used Tanner EDA tool to simulate the model. As seen in the results section of this work, the model is resistant to faults. The leakage current is reduced and is very less compared to traditional SRAM cells. The leakage power obtained with this model is $0.599 \mu \mathrm{~W}$ which is very less compared to the traditional methods. This model which we have proposed in this work, seems to be very much apt to density packed operations and also when power efficient operativity is required. This work tackled the basic issues of the traditional SRAM design, where R/W efficiency, leakage current and fault tolerance were taken into consideration. We were successful in achieving a system which provided solution to the above problems along with the issues of elevated temperatures, radiation, or EMI.