An FFT Accelerator IP Core Implemented on FPGA
Vamsi Krishna Challagundla, Jayaraj U Kidav, Shashank Kumar Singh, Anirban Jyoti Hati, Sai Kumar Mandiga · 2025
The main objective of this project is to design and implement a Fast Fourier Transform (FFT) IP core. Due to its ability to provide accurate frequency domain analysis of time domain signals, the FFT technique is indispensable in many applications related to digital signal processing. The implementation is based on the radix-2 method, whose lower computational complexity and hardware resource efficiency make it a good fit for FPGA platforms. With its robust FPGA and ARM CortexA53 processors, the ZCU104 board provides an adaptable environment for creating unique IP cores and incorporating them into more complex systems.The objective of this project is to use the Zynq SoC’s hardware acceleration capabilities to improve the FFT core for speed and resource consumption. The ZCU104 board is used to test and validate the built IP core, proving its usefulness for real-time signal processing applications. As compared to software-based FFT implementations, the results demonstrate a notable boost in performance, underscoring the potential of FPGA based solutions in high performance computing jobs.