Modified Booth Multiplier with Hybrid Adder
P. Cladien, Rayapudi Chandrika, V. Berlin Hency, O.V. Gnana Swathika · 2025
The basic goal of electronic devices is to deliver minimal power dissipation and fast speed in a compact footprint. Arithmetic operations determine the speed of electronic equipment. In many VLSI signal processing applications, multiplication is a crucial arithmetic operation. As a result, any signal processing module must have a high-speed multiplier. The literature has a vast number of multipliers. Array multipliers, Wallace tree multipliers, booth multipliers, Vedic multipliers, and Compressor multipliers are among them. The speed of these multipliers is determined by the quantity of partial product collected. In terms of multiplication speed, the hybrid parallel adder-based multiplier is offered as an improvement over the current approach. This method uses a hybrid adder to simultaneously add the partial products of two successive bits (multiplicands) (Weinberger and Ling adder). This paper proposes and designs a hybrid adder-based Modified Booth multiplier (CSELA) using the Ling adder and the Weinberger adder.