Multi-core Processor Chip Design for Complex Parallel Architecture
Yu Wang, Mingyong Xin, Changbao Xu, Jianyang Zhu · 2024
The current research on multi-core processor chips oriented to complex architectures has too much calculations when performing logic operations, and the problem of excessive power consumption leads to excessive power consumption. In order to solve the above problems, this paper studies a new multi-core processor chip oriented to complex architecture. By setting up 8 general-purpose computing units and the chip structure of the processor bus on the multi-core processor chip, using hyper-threading technology to achieve logical operations to increase the amount of calculation, calculating the power consumption of the multi-core processor chip, and analyzing the principles of power management control technology to achieve power Control, use the clock gating device to reduce the power consumption of the microprocessor chip, and complete the low-power design. And analyzed the power consumption of the chip in the logic operation process, and finally designed a low-power multi-core processor chip through the methods of power consumption calculation, power management control and dual-level clock gating of the multi-core processor chip. The experimental results show that the multi-core processor chip oriented to the complex parallel architecture studied in this paper can effectively reduce the amount of calculation when performing logic operations. Compared with before optimization, the power consumption is reduced to 1.5W, which has better practical application significance.