Response Time and Performance Analysis of Inter-Dependent Hard Real-Time Control Tasks Communicating Over a Predictable Publish-Subscribe Channel in MPSoC Platforms
Saeid Dehnavi, Dip Goswami · 2024
This paper explores the challenges and methodologies for analyzing the timing and performance of safety-critical real-time robotics and control applications on Multiprocessor System-on-Chip (MPSoC) platforms, i.e., CompSOC in this study. Leveraging a predictable Publish-Subscribe communication protocol, implemented based on a wait-free FIFO channel, we focus on the Worst Case Response Time (WCRT) analysis of interdependent hard real-time tasks in a processing chain, scheduled by a Timed Division Multiplexing (TDM) scheduler. For this purpose, after we define the execution model of Publish-Subscribe based real-time applications on CompSOC, we propose two distinctive WCRT analysis approaches: a deterministic calculation approach, and a stochastic approach based on Timed Automata (TA) theory and UPPAAL Stochastic Model Checker (UPPAAL-SMC) for a tighter WCRT bound. Moreover, building upon the stochastic TA model, we propose an approach for performance analysis, particularly focusing on factors such as message loss-rate and sensor-to-actuator throughput to present the percentage of the sample data that passes all the stages in the processing chain and affect the system behaviour. Our experimental validations, conducted on an implemented instance of the CompSOC MPSoC platform on the programmable logic (FPGA) of a Pynq board, affirm the effectiveness of our approach.