SystemVerilog Based Design of an RV32I Compliant RISC-V Processor Core
Abhinav Rajyan, Gaurav Saini · 2024
This paper presents the innovative design and implementation of an RV32I-compliant RISC-V processor core using System Verilog, aimed at advancing the understanding of RISC-V architecture through a modular and extensible approach. The design process involved the development and integration of critical components, including an Instruction Fetch module, Instruction Decode module, Register File, Arithmetic Logical Unit, Data Memory module, Control Unit, and Branch Control Unit, all seamlessly integrated into a top-level interface. Rigorous testing and verification procedures were conducted, demonstrating the processor core's capability to execute a comprehensive subset of the RISC-V instruction set with high reliability and efficiency. The modular design not only ensures robust functionality but also provides a scalable foundation for future enhancements, such as the incorporation of complex instructions and multi-cycle operations. The results affirm the processor's operational integrity and highlight its potential for further architectural innovations in RISC-V processor design.