LLM vs HLS for RTL Code Generation: Friend or Foe?
Sutirtha Bhattacharyya, B G Sutharshanan, Chandan Karfa · 2024
High-Level Synthesis (HLS) tools are widely used for the efficient transformations of behavioural code into equivalent hardware in Register Transfer Level (RTL). However, recent studies show that Large Language Models (LLMs) can be used to generate Verilog or equivalent hardware descriptions directly from behavioural descriptions, making LLMs a potential ‘foe’ for HLS. While LLMs can generate RTL code, they lack certain fine aspects like control over design constraints and optimizations and the inability to handle large behavioural designs. In this paper, we show how LLM can be a ‘friend’ of HLS in generating RTL directly from behavioural descriptions. Although HLS tools have matured over the years, making the input code synthesizable, applying correct pragmas and source code optimizations are still manual efforts in the HLS. LLMs can make hardware accelerator design with HLS easier by automating these manual steps. We show that LLMs are efficient in resolving synthesis issues and optimizing course code for HLS. We have used performance to hardware gain to evaluate the LLMs’ performance in optimizing code adhering to resource usage. We perform our experiments on image processing tasks as benchmarks and discuss where LLM can perform well as well as the issues faced by it when trying to maximize the performance to hardware gain.