A Transmission Gate Based BCD To Seven-Segment Decoder with a Power Consumption of 6.03626 $\mu \mathrm{W}$
Fuad Hasan, Richard Victor Biswas · 2025
In digital electronics, Binary Coded Decimal (BCD) to Seven-Segment Decoders are essential tools for converting BCD input into an output seen on a seven-segment display. This paper undertakes a comparative analysis of the proposed system utilizing 45nm bulk MOSFET technology through three different methods: Complementary Metal-Oxide-Semiconductor (CMOS), Pseudo NMOS Logic and Transmission Gate. A detailed analysis and comparison of the design process and important aspects of each technique is conducted, with a particular emphasis on important metrics such as propagation delay and power consumption. After a successful comparison, it can be concluded that transmission gate based technology achieves the best performance in power consumption, measured at 6.03626$\mu \mathrm{W}$. Additionally, it demonstrates a frequency of 126.87 MHz and a propagation delay of 200.41 ns. Furthermore, we conducted three sign-off processes, for example, Layout Versus Schematic (LVS), Electrical Rule Checking (ERC) and Design Rule Checking (DRC) tests, revealing a layout area of 406.1686$\mu \mathrm{m}^{2}$using the transmission gate technique. To validate the proposed design, we carried out (Process, Voltage, and Temperature) PVT Corner analysis & Monte Carlo simulation in Cadence Virtuoso.