RAPID: Re-configurable Adder Tree based Performance-Incentivized AI Digital CIM Macro
Akash Sankhe, Narendra Singh Dhakad, Radheshyam Sharma, Mukul Lokhande, Santosh Kumar · 2025
Rapidly rising AI applications have driven the need for energy-efficient and high throughput SRAM-embedded CIM macro. This article proposes RAPID-CIM, a novel reconfigurable digital CIM with M8T bitcell, an area-efficient hierarchical adder tree to address drawbacks associated with the performance in conventional SoTA works. The proposed architecture achieves a maximum of up to 16.7× improvement in energy efficiency and an 8.6× enhancement in compute density compared to state-of-the-art (SoTA) designs at CMOS 65nm. RAPID-CIM achieves superior performance for diverse AI workloads with scalable bit-precision and sparsity-aware operations, reducing up to 3.2× operation cycles and a 30% memory bank usage and application accuracy within 97.8% Quality of Results (QoR). Thus, the proposed solution is well-versed optimization for resource-constrained Edge-AI platforms.