Power Optimized Carry Select Adder Using Reversible Logic Gates
D. Rohini, M. Harsha Vardhan Reddy, G. Kishor · Advances in engineering research/Advances in Engineering Research · 2025
Reversible logic is playing an important role for low power computations.In today's trend it is essential to optimize the power for portable devices which can be achieved through reversible logic computation.The low power computations can be performed using Reversible Logic Gates (RLG) which forms the fundamental blocks of the digital logic circuits.One of the important metric's in the integrated circuit design is Power dissipation.The Digital circuits constructed using irreversible conventional logic gates dissipates more power when compared to the circuits with Reversible Logic Gates.Adders are the fundamental components which performs the basic addition operation in many complex calculations.Among various adders available Carry select Adder being the fastest adders used to perform the basic arithmetic Addition operation in many data processing processors.Thus it is essential to design a power efficient Carry select Adder(CSA) in power constraint and high speed design applications.In this paper both conventional and reversible CSA is modelled using Verilog HDL and it is synthesized by using XILINX VIVADO EDA tool.