Securing RISC-V Processor Using Randomized Scan Obfuscation
K Badarinath, N. Mohankumar · 2024
Recent attacks on existing logic encryption methods seek to extract secret keys, raising concerns about the overall security of integrated circuits (ICs). Prioritizing the safeguard of the Design-for-Test (DIT) infrastructure is crucial. In the face of evolving security challenges in logic encryption, it is essential to maintain the integrity and confidentiality of intellectual property. Robust protection against various attacks like SAT, sensitization, bypass attacks etc., is necessary. In this paper, Randomized Obfuscation system that use dynamic scan obfuscation to obscure the scan process and prevent unwanted attempts at scan access. The efficacy of the suggested secure Design-for-Test (DIT) infrastructure is demonstrated by a thorough security study. The proposed method is incorporated on to a RISC-V processor to secure the design. The design overheads and security evaluation metrics namely Hamming distance and output corruption results highlight our claim of securing the RISC V processor at less design overhead.