Enhancing AES Security and Performance: A Novel 8-bit Architecture with Unique Key Expansion for IoT Applications
R. Sudharshan, Yogesh P, A. Prathiba · 2024
The Advanced Encryption Standard (AES) is widely recognized as the standard for securing various applications and services. In this paper, we introduce a novel AES architecture that features an 8-bit data path and a unique key expansion architecture. This novel key expansion significantly enhances the security of the design, ensuring robustness against attacks and also increases the operational frequency on both FPGA and ASIC implementation. Our AES implementation efficiently completes its operations in 160 clock cycles, showcasing its superior performance. When implemented on a Xilinx FPGA board, our design achieves a maximum operating frequency of 136 MHz. On 180nm technology using Cadence Genus, it operates at 104.6 MHz. These frequencies represent a substantial improvement over existing 8-bit AES designs, resulting in higher throughput. The enhanced security of our design requires at least 232 attempts to guess the original key, making it ideal for IoT real time applications where security and power efficiency are paramount. This novel architecture not only improves speed and throughput but also ensures that security is not compromised.