Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects
Ya-Rou Hsu, Aaron C.-W. Liang, Han-Ya Tsai, Yen‐Ju Su, Charles H.‐P. Wen, Hsuan‐Ming Huang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
Cell layout generation plays a crucial role in design automation. The generated layout must not only adhere to design rules but also exhibit optimized performance in terms of factors such as delay, power, area, and cost. However, prior works often rely on metrics that fail to consider the layout-dependent effects (LDEs). Furthermore, evaluating the actual performance using commercial tools can be excessively time-consuming, especially when iteratively optimizing cell layouts. Therefore, this work proposes a new machine-learning(ML)-based ranking model to enable rapid performance ranking between layout candidates of standard cells. This model incorporates all LDEs in feature extraction, generating an ordered list of cell layouts, and evaluating only the top-Kcandidates for performance. The experiments show that this approach successfully identifies the optimal layout from ten benchmark cells, which are most used in intellectual property (IP) cores, in a sub-5 nm fin field-effect transistor (FinFET) industrial standard cell library, achieving a$348\times $speedup over the conventional flow.