Design and Implementation of a Digital Amplitude Demodulator using FPGA
Kamal Aboutabikh · IMRJR · 2025
In this paper, we propose the design and implementation mechanism for a digital amplitude demodulator based on the use of Direct Digital Frequency Synthesizer (DDFS) and digital filter using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1.The proposed demodulator has the following parameters: =50MHz.CLK F frequency: Clock -/ K=50000 KHz /1250 =40 KHz ).CLK : (fsam= F KHz 40 fsam= : frequency Sampling --Cut-off frequency of the low pass filter (LPF): fcut=2 KHz -Modulation type of signal is: AM, LSB with carrier, USB with carrier.-The modulating signal is sinusoidal of frequency: fmod=1 KHz , fmod=1.5 KHz ( fmod<= fcut ).-Carrier type: is sinusoidal with frequency: fcar=10 KHz.-The ROM capacity for the stored signal samples 8192X8 bits, and their values are positive within the range from 0 to 255.-Frequency range: (3 Hz…25 MHz).-Frequency Resolution: (3 Hz).-Signal amplitude (5V).-Digital designs allow the slides to modify and design development for results and better!!! through reprogramming, depending on the user's desire.