Optimizing Semiconductor Testing: Leveraging Stuck-At Fault Models for Efficient Fault Coverage
Vijayaprabhuvel Rajavel · International Journal of Latest Engineering and Management Research (IJLEMR) · 2025
With the increasing scale of computing systems and the growing complexity of modern processor architectures, the importance of in-field testing mechanisms continues to rise.Traditional scan methods and automatic test pattern generation (ATPG) are often too resource-intensive or ineffective when adapting to long test programs and out-of-order execution cores.This study proposes an automated Software-Based Self-Testing (SBST) method for RISC-V cores based on reinforcement learning (RL).The key contribution lies in the use of toggle coverage as a proxy metric, significantly reducing computational overhead during RL agent training while maintaining a high level of stuck-at fault detection.Experimental results on synthesized RISC-V cores (both in-order and out-of-order) demonstrate that the proposed RL-SBST approach achieves over 90% stuck-at fault coverage with relatively short test programs (approximately 200 instructions), significantly outperforming random strategies and RISCV-DV-based techniques (an automated test generation method that combines features of the RISC-V architecture with dynamic fault dependency models for optimized and efficient defect coverage).This study highlights the potential for integrating RL algorithms and proxy metrics to optimize infield testing of computing devices without requiring significant hardware modifications or increasing system downtime.The findings are relevant to researchers and practitioners in microelectronics, automated testing, and fault modeling.