Privacy Enhanced PYNQ-Z2 based IoT Edge: NTT Performance Analysis
B Sathiya Naraayanan, Haribabu Pasupuleti, Sasirekha GVK, Jyotsna L. Bapat, Debabrata Das · 2024
Edge based architectures for IoT have the advantages of reduced bandwidth requirements, low latency for decision making, and privacy, by confining the data to the Personal Area Networks (PANs) and within the edge. However, to exploit the high computational power and storage capacity of the cloud services, it is required to send data periodically beyond the edge. Homomorphic Encryption (HE), a method by which operations are possible on encrypted data without decryption, can be used at the edge to ensure PAN data privacy. In this paper, a privacy enhanced architecture of edge device using a PYNQ-Z2 FPGA board has been presented. A novel architecture is proposed wherein, NTT, a most computationally intensive function of HE, is performed in hardware. The scenario where HE is required at the edge has been presented. The performance of this NTT in hardware has been evaluated from computational time perspective. The results show computation time is cut down to 14.7% of pure software implementation in Programming System (PS) of the PYNQ-Z2. Additionally, the comparison with modulo operation of the NTT in hardware, as was earlier proposed in literature, is done. The resource constraints and performance are described as a part of the results.