37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability
David Wolpert, Gerry Strevig, Chris Berry, Leon Sigal, Bill Huott, Mark Cichanowski, Matthias Pflanz, Tobias Werner, Philipp Salz, Nick Jinq, Michael Romain, Iris M. Leefken, Richard Serton, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Stefan Hougardy · 2025
The IBM zNext's Telum II processor [1] is a full-stack overhaul of its predecessor [2], featuring a modified 5nm Samsung bulk technology [3], new IBM-created standard cell and IP libraries, and a variety of further design-technology co-optimizations (DTCO). While die size grew from$530\text{mm}^{2}$to$600\text{mm}^{2}$(1.13×), each chip in the dual-chip module became denser, featuring 1.3T shapes (1.25×), 43B transistors (1.38×), and 38km of wire (1.28×) across 18 BEOL layers. As IBM's first 5nm processor, Telum II was a concurrent hierarchical design effort, with libraries, IP blocks (array / regfile / analog / phy / custom), and all gate-level entities designed simultaneously. These data volume and concurrent design pressures drove a variety of abstraction, modeling, and other EDA innovations in addition to those involving power, performance, area, and reliability targets.