A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri, Teja Masina, Kuo-Cheng Lin, Po‐Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming‐Hung Chang, C.C. Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping Wei Wang, Geoffrey C-F Yeap · 2025
Embedded memories are crucial SoC design components; among these, SRAM plays a vital role in enhancing system performance across various applications. The ongoing demand for high-capacity on-die SRAM necessitates optimal-density scaling as we transition technology nodes. In mature technology nodes, reducing the bit cell area significantly contributed to SRAM scaling. However, as we move into more advanced technology nodes, scaling the cell area becomes increasingly challenging. Design-technology co-optimization (DTCO) becomes essential to achieving further area scaling at the chip level. We focus on optimizing both cell and peripheral designs to improve memory density. Our SRAM design leverages the unique characteristics of 2nm nanosheet technology. We also explore various design domains, such as SRAM macro architecture, design assist techniques, and floor planning. The primary objective of this paper is to minimize the periphery while maximizing the bit cell array size. This is achieved by increasing the number of bit cells per BL, as the 2nm nanosheet technology improves the cell's on-to-off current ratio. This advancement allows for a 2× increase in the maximum BL loading compared to the previous technology. Additionally, we implement special logic rules, for the peripheral logic, to further optimize its area, as illustrated in Fig. 29.1.1(a).