Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model
Fahad Rahman Amik, Yousef Safari, Zhanguang Zhang, Boris Vaisband · 2025
Early-stage timing analyses are essential for exploring design alternatives before physical synthesis in integrated circuit design, which needs to assess signal propagation delay multiple times with varying accuracy. Machine learning (ML) offers promising solutions for early-stage timing prediction, improving result quality while reducing runtime, time-to-market, and non-recurring engineering costs. However, existing ML-based approaches for predicting timing at the register-transfer level (RTL) are not sufficiently reliable to replace traditional electronic design automation tools as they face two key challenges: 1) feature generation based on high-level RTL is unreliable due to unpredictable synthesizer outputs, and 2) they omit essential features like technology library information and design constraints, which are crucial for accurate timing analysis.