HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications
Shangli Li, Mingjie Xing, Yanjun Wu · 2025
CGRA(Coarse-Grained Reconfigurable Architecture) is characterized by high energy efficiency and reconfigurability, plays an important role in various complex applications. However, current CGRA compilers only handle simple inner loops and struggle with complex nested loops, making it hard to deploy large-scale complex applications on CGRA for acceleration. Therefore, we proposed a hierarchical dataflow compiler HDCC based on MLIR[1] to deal with complex loop structures in layers and developed a tool for generating dataflow graphs from MLIR intermediate code to capture the dataflow of complex loop structures. We also propose a method to deploy large-scale applications to CPU-CGRA with HDCC.The experimental results show that HDCC is capable of deploying large-scale complex applications such as neural network tasks and cryptographic tasks onto CGRA, achieving up to 11.4× performance improvement on these tasks.