Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis
Md Imtiaz Rashid, Benjamin Carrión Schäfer · 2025
This work introduces a complete flow to make legacy, side-channel attack (SCA) unaware, hardware given as an Register Transfer Level (RTL) description (Verilog) secure through an RTL to C compiler that generates optimized C code for High-Level Synthesis (HLS). This compiler analyzes the legacy RTL description against SCA and generates C code that can then be in turn re-synthesized into new RTL code that is security-aware. Experimental results show that our proposed flow is able to make security unaware RTL code secure introducing minimal overheads.