Efficient and Secure Cloud-based Split Logic Synthesis
Chaitali G. Sathe, Yiorgos Makris, Benjamin Carrión Schäfer · 2025
This work introduces a secure split logic synthesis (cloud+local) approach to enable Third Party Intellectual Property (3PIP) vendors that do not have access to expensive state-of-the-art logic synthesis tools to efficiently and securely synthesize their IPs with minimal area and delay overheads. For this, we propose to split the Register Transfer Level (RTL) IP given in Verilog or VHDL such that one part is synthesized on the cloud using a state-of-the-art commercial logic synthesis tool (e.g., Synopsys Design Compiler) while synthesizing locally, on the IP vendor's side, the missing portion of the design using free logic synthesis tools (e.g., Yosys). This approach allows 3PIPs to leverage the power of commercial logic synthesis tools while protecting their IP from anyone having access to the cloud where the logic synthesis tools is hosted without fearing that the IP will be stolen. Experimental results show that our proposed flow is secure, while leading to negligible area and delay overheads. In particular, the proposed flow has an average area overhead of 0.94% to 1.81% for different types of design implementations and in all cases the original timing constraint is met.