TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level
Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa · 2025
Power Side-Channel Attacks (PSCAs) are a significant threat to modern cryptographic hardware. The overall power consumption of the target device can be passively probed to obtain the secrets being processed by its underlying cryptographic algorithm. Several countermeasures have been formulated to secure hardware implementations of cryptographic algorithms against such attacks. The objective of such countermeasures is to reduce the correlation between secret data being processed and the power consumption (the side-channel) of the device under attack. In this work, we propose an automated, circuit transformation-based ad-hoc countermeasure against PSCAs at the Register-Transfer Level (RTL). By analyzing sensitive registers within the device we propose a method that duplicates sub-circuits influencing the output of these sensitive registers. Additionally, register pushing and balancing, and clock gating are applied adequately to aid further obfuscation. As demonstrated through our experiments on the state-of-the-art ciphers PRESENT and AES's S-boxes, these approaches were found to be quite effective in randomizing the power consumption and reducing the dynamic power consumption of the circuits. Standard TVLA test of our protected circuits against the unprotected implementations show a significant increase in the effort for univariate PSCA attacks.