SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation
Jugal Gandhi, Nikhil Handa, Abhay B. Nayak, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey · 2025
The modern distributed chip design chain is increasingly vulnerable to piracy and overproduction. Logic locking has emerged as a prominent solution, allowing chip designers to enhance the security of their hardware intellectual property (IP) by obscuring the functional behavior of the design. Multiplexer (MUX)-based locking is notable for its effectiveness and efficiency. Recent studies have identified its susceptibility to Boolean satisfiability (SAT) and structural learning-based attacks. This article addresses security vulnerabilities and introduces a secure hardware IP design technique with key-controlled cascade gated MUX-based locking (SHAKTI) and its variant SHAKTI+. The proposed techniques integrate a daisy-chained structure and MUXes to improve attack resilience while optimizing resource overhead. The experimental results on ISCAS'85 and ITC'99 benchmark netlists with 64-bit and 128-bit key sizes demonstrate the average area/power/delay overheads for SHAKTI and SHAKTI+are 19.32/16.35/11.86% and 19.45/17.60/11.56%, respectively. Security evaluations against the SAT attack demonstrated timeouts for all netlists, obstructing key recovery. The average key prediction accuracy for the SCOPE attack on SHAKTI and SHAKTI+locked designs is only 20.90%. To extend the evaluation, power trace analysis of the locked netlist shows a key-aliasing effect across most locked netlists. The proposed techniques achieve a balanced overhead-security trade-off, strengthening locking against oracle-guided and oracle-less adversarial models.