Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSD
Pikul Sarkar, Nitin Gupta, Pallat Aravind, Bhavin Odedara, Dror Shahar · 2025
SSD (Solid State Drives) controllers communicate between hosts with high-speed interface like PCIe and NAND flash arrays. It gets data from host and transfer them to NAND and vice versa. To perform these operations, the controller needs highly accurate high-speed clocks for sustained performance. These clocks are generated by a clock multiplier circuit like PLL which requires an accurate reference clock. In general, a crystal oscillator (XTAL) is used to provide it, but it incurs BOM cost and increases PCB design complexity. Though the host transmits a clean clock along with the data, it may turn it off before the controller has finished transferring the data to NAND. This work presents a novel design by which this host clock is multiplexed with an internal relaxation oscillator clock to always provide a clock to the PLL. The control logic ensures that the output clock is always available by selecting between the input clock and the internal clock without any external indication and any frequency glitch. Thus, the PLL runs at highest accuracy when new data is coming in and is available at a lower accuracy to complete back-end operations when data stops. This enables the SSD to remove the XTAL and reduce the cost and complexity. The design was implemented in TSMC 7nm with 0.036 mm2 core area and was validated in lab.