NSGA-RM: NSGA-II Evolved Performance Optimized Non-Homogeneous Recursive Polynomial Multiplier Architectures
Daksh Sharma, D R Vasanthi, Sanampudi Gopala Krishna Reddy, Madhav Rao · 2025
Implementing hardware-efficient and high-performance polynomial multiplication in finite fields is crucial for enhancing crypto-systems on silicon, which is desirable for system-on-chip (SoC) applications. The recent developments, such as hybrid recursive multiplier (HRM) design leverage state-of-the-art various (SOTA) multipliers, M-Term Non-Homogeneous Karatsuba Multiplier (MNHKA), and M-Term Non-Homogeneous Overlap-Free Karatsuba Polynomial Multiplier (MNHOKA). However, HRM design explores the design space heuristically, which may not always yield optimal solutions. To overcome this limitation, a novel Non-dominated Sorting Genetic Algorithm Recursive Multiplier (NSGA-II-RM) technique is proposed over exhaustive design space exploration to achieve the most optimal solution. By applying NSGA-II optimization technique, the design process systematically explores a wide array of potential recursive-multiplier (RM) configurations, across multiple contrasting hardware parameters. The design solutions generated through multiple runs of NSGA-II algorithm are synthesized using the Cadence Genus tool for GPDK 45nm technology node. The best Optimal-front solution offers a 24.65% footprint saving, a 6.71% improves critical path delay, area-delay-product (ADP) gain of 29.71%, power savings of 40.65%, and a salient 34.32% improvement in Power-Per-Area (PPA) compared to the cutting-edge designs of MNHKA, MNHOKA, and HRM. All the design files are made freely available for easy adoption and further usage to the researchers and designers community.