Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency Synthesizers
Abhinav S, B. R. Karthikeya, Ishan Acharyya, Anushka Tripathi, Abhishek Srivastava · 2025
This paper presents the design of a dynamic hybrid adder for high speed, low-power MASH 1-1-1 Delta Sigma Modulator (DSM), which is commonly used in low noise fractional-N frequency synthesizers. The proposed high-speed hybrid adder architecture employs Carry-Look-Ahead and Carry-Select adders to achieve superior worst-case delay performance as compared to the previously reported works. Implementation of the proposed hybrid adder utilizes Domino Logic style and Manchester Carry Chain adder topology. Additionally, a negative-edge triggered partially static, low-power, high-speed hybrid flip-flop is also presented to sample the adder output before its pre-charge phase. The proposed designs have been simulated and synthesized in Verilog using Xilinx Vivado 2024.1 on Zedboard. Mash 1-1-1 DSM design with the proposed adder is also implemented in TSMC 65nm CMOS technology. Simulation results show that the proposed adder achieves a worst-case delay of 181.9 ps and an average power consumption of 202.52 μW, at a clock frequency of 100 MHz. The Mash 1-1-1 DSM design, utilizing the proposed adder, was simulated to achieve specific average values at a clock frequency of 100 MHz across various process and temperature variations and compared with measured average values.