PUF-Secured Memory: Integrating Arbiter PUFs with Error Correction for Memory Protection
C. S. Anusree, Gokula Kumaran K. G., C. S. Saisudharshan, Sappa Saran, N. Mohankumar · 2024
This paper presents a new method for protecting memory intellectual property by adding an Arbiter Physical Unclonable Function to the error correction application of the memory read access circuits. We use the unique features of hardware-based PUFs to create an authentication technique, which ensures that the memory IP cannot be copied to different hardware. The PUF is integrated into the error correction circuit, serving both security purposes and its main function. The PUF generates a unique signature for the read operation to validate the hardware. If the circuit is copied on different hardware, the PUF authentication fails and the copied PUF generates fake data, making the copied IP inaccessible. We ensured that the adapted error correction circuit provides no reduced effect for any correct operation. The model of the integrated PUF-based error correction circuit, its security evaluation, performance analysis are presented in the paper. Our contribution to security is in offering a practicable method for protecting memory IP, which is vital since hardware piracy is becoming an increasing issue in the semiconductor industry.