Design of a Simplified Floating Point Adder for Complex Computation
P S Vanashree, Rohan S Belgumpi, M B Veena · 2024
A new highly efficient floating-point adder/subtractor has been refined to enhance the efficiency of both addition and subtraction processes. This design emphasizes a streamlined architecture for quick computation with power efficiency. One important feature of this adder/subtractor is its simplified structure that enhances floating-point arithmetic and reduces power consumption. Despite including a subtraction circuitry, the compact design makes it suitable for high-performance computing environments. Such an adder/subtractor is essential in financial modelling as it processes vast amounts of complicated numerical data to predict market trends. It also serves scientific research by providing trustworthy and effective arithmetic solutions thus enabling data analysis and simulations. The power consumption goes down by 4.153W, the LUT (area) goes down to 189, and computational efficiency increases tremendously compared to traditional methods. This versatility, better performance, and power efficiency make the design valuable to different industries, which offer benefits such as reduced topology complexity and optimized mathematical manipulations.