Power, Performance, and Area Optimisation of the RISC-V Processor
Anushka Ganguly, Arindam Chakraborty, Abhijit Ambekar, Hemanta Kumar Mondal · 2024
RISc-V is a processor core designed according to an open standard instruction set architecture (ISA). Its architecture is important in the world of computing due to its scalable and customisable design., along with its precision. The processor finds its application across various domains., which presents complex challenges related to the tailored requirements of capabilities. In this paper., an endeavour has been made to optimise the power., performance., and area of the processor core by implementing design strategies to increase the clock frequency by 50% and reduce the die area by 3 %.