Implementing a Transputer for FPGA in Less Than 800 Lines of Code
Carl‐Johannes Johnsen, Kenneth Skovhede, Brian Vinter, Lindsay Quarrie, Dickson Larry · IOS Press eBooks · 2019
By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ~4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.