VHDL Generation from Python Synchronous Message Exchange Networks
Asheim Truls, Kenneth Skovhede, Brian Vinter · IOS Press eBooks · 2018
The Synchronous Message Exchange, SME, is a programming model that both resembles communication in hardware, and can be implemented as a CSP network. This paper extends on previous work for modeling hardware-like programs using SME in Python, with the addition of a source-to-source compiler that converts an SME network implemented in Python to an equivalent implementation in VHDL. We describe the challenges, constraints, and solutions involved in translating a highly dynamic language like Python into the hardware-like VHDL language. We also show how the approach can assist in further VHDL refinement by generating tedious test bench code, such that VHDL designs can be simulated and verified with vendor supplied simulation and synthesis tools.