T42 – Transputer Design in FPGA (Year Three Design Status Report)
Mielke Uwe, Zabel Martin, B.W. Michael · IOS Press eBooks · 2019
Our IMS-T425 compatible Transputer design in FPGA has so far taken over 300 design days. Up to last year, minimal effort was spent for verification. Now a regression test bench has been brought in place, which is targeted to verify the design conformance after any changes. This T42 Transputer Verification Suite is based on a TVS-1 work from Michael Bruestle, and compares the register output of 54 selected instructions versus a true T425 golden reference for up to thousands of data samples. It has already helped in T42 micro-code debugging and hardware refinement.