Investigation of Cell Variation Effect on Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory
Sangmin Ahn, Hyungjun Jo, Sechun Park, Jongwoo Kim, Hyungcheol Shin · IEEE Transactions on Electron Devices · 2025
In this article, we investigated the effects of cell variations, specifically the variations in gate length (${L}_{\text {g}}$), spacer length (${L}_{\text {s}}$), filler oxide thickness (${T}_{\text {f}}$), channel thickness (${T}_{\text {ch}}$), tunneling oxide thickness (${T}_{\text {tox}}$), charge trap nitride thickness (${T}_{\text {ctn}}$), and blocking oxide thickness (${T}_{\text {box}}$), on the z-direction interference (Z-interference) in charge-trap-based 3-D NAND flash memory. Most previous studies have primarily focused on Z-interference degradation caused by the physical scaling of Z-dimensions, which has become a major obstacle in developing advanced multilevel cell technologies such as quad-level cell (QLC) and penta-level cell (PLC). However, with the physical scaling issue, the limitations of the fabrication process are causing cell variation. Nevertheless, research on Z-interference resulting from cell variation remains insufficient in existing studies. Therefore, we analyzed the impact of cell variation on threshold voltage (${V}_{\text {th}}$) distribution through the Monte Carlo simulation, incorporating technology computer-aided design (TCAD) and experimental data. These results not only offer a comprehensive understanding of Z-interference but also provide valuable insights for formulating process design guidelines.