An Improved Parallel Adder
Yanding Wang, Shan Ouyang · 2024
This paper presents an improved parallel adder. Based on the achievements of parallel adders developed by the team of Ternary Optical Computer(TOC), this adder introduces variable distance shifting technology, which eliminates the intermediate result storage operations in memory, thereby reducing the memory access time during the entire addition process and enhancing the operational speed of the adder. To validate the feasibility and advancement of this research, we established a corresponding experimental platform on Field-Programmable Gate Array(FPGA) and compared the performances of the two adders. Experimental results indicate that the improved parallel adder significantly outperforms the original parallel adder, demonstrating that the variable distance shifting technology effectively enhances the computational efficiency of the parallel adder.