Coevolution of Chiplet Technology and Cache Architecture for AI and Compute
John Wuu, Mike Mantor, Gabriel H. Loh, Alan P. Smith, Dave Johnson, David Fisher, Brett C. Johnson, Carson Henrion, Russell Schreiber, Jeff Lucas, Stephen Dussinger, Alistair Tomlinson, Will Walker, Paul Moyer, Deepak Kulkarni, Daniel Ng, Wonjun Jung, Raja Swaminathan, Samuel Naffziger · 2024
Last level cache (LLC) is an important component to processor compute performance. As it often occupies a non-trivial percentage of SOC die area, it presents co-optimization opportunities with chiplet technology development. On the CPU side, server LLC advances culminated in the hybrid-bonded AMD 3D V-Cache™, for which highlights from the first and second-generation products are summarized. On the GPU side including AI accelerators, the progression of the AMD Infinity Cache™ LLC from planar to 2.5D chiplets to 3.5D integration is tracked. The products combine to showcase the possibilities that symbiotic co-development between cache architecture and chiplet technology can realize in further propelling AI and compute performance.