Context Aware Deep Learning-Based Fault Localization for Hardware Design Code
Jian Hu, Zhenlei Liu · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
Fault localization is a technique that plays a valuable role in reducing the burdensome task of hardware design code, such as Verilog or VHDL. The recent advancements in deep learning have demonstrated significant progress, showcasing the promising potential of various neural network architectures in comprehending and extracting meaningful insights from data. Importantly, this potential offers a new perspective that could potentially benefit fault localization techniques. In this article, we proposed Carpel: a context aware deep learning-based fault localization method for hardware design code. First, a dynamic execution coverage matrix and an error vector are generated by simulating the hardware code with various stimuli. Subsequently, a failing context is established to narrow the search space for fault localization. Next, three customized deep neural network models are developed and trained using the context-aware coverage matrix and error vector. Finally, a virtual test set is employed to these models to assess the suspiciousness of each statement. Experimental results indicate that our method outperforms state-of-the-art dynamic fault localization techniques, namely, Detraque, Tarsel, and Cirfix. Specifically, our approach identifies 37.03%, 22.22%, and 33.33% more faults than Detraque, Tarsel, and Cirfix, respectively, using the top-1 metric.