An Implementation of a DSP-Based PAM-4 Digital Equalizer with 32-Way TI-ADC
Sang-Hyeon Ok, Dong-Hoe Heo, Joosun Lee, Seung-Mo Jin, Kwang‐Ho Lee, Daniel J. W. Jeong, Min-Seong Choo · 2025
This paper presents an ADC-based digital equalization architecture designed for high-speed wireline communication systems under PAM-4. The system integrates a 32-way time-interleaved 7-bit SAR ADC with following a 14-tap feedforward equalizer (FFE) using sign-sign least mean square (SS-LMS) adaptation and a 1-tap decision feedback equalizer (DFE). It also includes a continuous-time linear equalizer (CTLE) and a bit-error rate tester (BERT) for performance validation. The proposed design addresses the challenges of long-distance transmission over lossy channels by minimizing intersymbol interference (ISI) and improving signal integrity through adaptive equalization.