Design of Adder-based DA-OBC using inner product computation for memory-efficient architecture
Kiran Kumar Bhadavathl, Z. Mary Livinsa · 2025
This paper presents a new Adder-based DA-OBC (AB-DA-OBC) design that is memory-efficient, as well as high-order filters utilizing the DA-OBC architecture that eliminates a look-up-table (LUT). The recommended AB-DA-OBC architecture’s memory utilization in half at each iteration of LUT minimization for finite impulse response (FIR) filter. The suggested AB-DA-OBC is for traditional and modern hardware designing and is effective for both VLSI as well as FPGA applications. The memory reduction technique effectively regulates hardware use between logic elements (LE) and memory and substantially expands the maximum amount of filter orders that may be implemented on FPGA architecture. The proposed AB-DA-OBC architecture saves 29.46% of logical elements and 35.85% of memory LUT based distributed arithmetic, also saves 35.84% throughout the LUT less DA-OBC according to the FPGA execution, this method allows for a more efficient implementation of FIR filters in distributed arithmetic systems.