Development and Realization of a Multi-Rate FIR Filter Utilizing Distributed Arithmetic on FPGA
Jerome Albert A, Jenifer Gloria Daphne, S. Vigneshwaran, Karuthapandian Mariammal · Journal of Electrical Engineering and Automation · 2025
This research presents an efficient development of a multi-rate Finite Impulse Response (FIR) filter utilizing Distributed Arithmetic (DA) for digital signal processing (DSP) applications. The motivation behind this work lies in the increasing demand for high-performance filters in various multimedia and communication systems, where low power consumption and area-efficient designs are critical. The proposed FIR filter utilizes DA to minimize the resource requirements typically associated with conventional filter implementations while achieving comparable or improved performance metrics. A Look-Up Table (LUT) based approach is employed to compute filter outputs, allowing for rapid and efficient processing of input samples. Simulation results demonstrate that the multi-rate FIR filter significantly minimizes the computational complexity and enhances speed, Optimizing it for real-time performance in embedded systems. The findings emphasize the significance of integrating Distributed Arithmetic into FIR filter designs., paving the way for more advanced signal-processing solutions in VLSI architectures. This proposed design is implemented using Vivado version 2023 in Zynq UltraScale + MPSoCs family.