Design of an array multiplier in PFSCL style
Journal of Information and Optimization Sciences · 2025
In intergreted circuit design, the current trend is to create circuits that work well for both digital and analog (mixed signal) applications. The PFSCL has been a optimum choice in these applications. This paper proposed three different architectures of 2-bit array multiplier in PFSCL style. The architecture-1 uses PFSCL NOR/OR gates, the architecture-2 uses PFSCL Fundamental cell (FC), and the last architecture-3 integrates memristors with PFSCL design circuit. All proposed architectures are simulated in LT Spice tool with 90nm PTM technology. Out of all the proposed architectures, architecture-3 observes the most efficient in all the performance parameter. The proposed architecture-3 observes maximum reduction of 39 %, 66 % in paramter like delay and power consumption respectively, additionally, offers a maximum area saving of 97 % as compared to proposed architecture-2.