Reconfigurable and delay reduced level shifter for multi process FPGAs
A - Nedha, Er. Senthazai -, Er.Madhan -, P - Nivetha, Sulthana Begam S - · International Journal on Science and Technology · 2025
Traditional level shifter circuits often suffer from significant propagation delays and power overhead, which limits their performance in high-speed and low-power applications. In response to these challenges, this work introduces a reconfigurable and delay-reduced level shifter circuit specifically designed to improve interoperability between multiple voltage domains in FPGA-based systems. The proposed circuit leverages adaptive threshold control and optimized transistor configurations to minimize delay without compromising signal integrity, ensuring efficient voltage level translation across varying voltage domains. These advancements make the circuit particularly well-suited for dynamic voltage scaling (DVS) and heterogeneous computing environments, where the system operates under varying power and performance conditions. The reconfigurability of the circuit allows for its adaptation to different system requirements, providing a flexible solution for multi-process FPGAs. Additionally, by reducing both delay and power consumption, the proposed level shifter enhances the efficiency of power-aware FPGA designs, extending their applicability in real-time and embedded systems that demand high performance and low energy usage. This innovation promises to significantly improve the viability of FPGA systems in a wide range of modern, energy-conscious applications.