Design and verification of 16 & 32-Bit CPUS using ARM architecture
Ammisetty Mahesh Babul, Krishna Veni Sahukara, Naga Sai Gopal Vadapalli Venkata, Chanakya Pukkalla, Harsha Amalakanti, Sri Harshita Ganti · 2025
This paper presents the design and implementation of scalable CPU architecture, available in both 16-bit and 32-bit configurations, inspired by ARM’s efficient and versatile microprocessor designs. The primary objective is to create a processor capable of executing ARM instruction sets while offering adaptability to various application requirements. The design process involves the integration of key components such as the instruction fetch unit, microarchitecture, control unit, arithmetic logic unit (ALU), and memory interface, all aimed at optimizing performance, power efficiency, and ease of programming. The architecture is meticulously designed to balance high performance with low power consumption, making it ideal for embedded systems and Internet of Things (IoT) devices. Detailed simulations validate the CPU design, ensuring accurate functionality and reliable operation. Additionally, the processor is synthesized for FPGA implementation, providing a practical demonstration of its capabilities in real-world scenarios. The results highlight the feasibility of leveraging ARM architecture principles to develop compact, powerful CPUs that can efficiently handle a wide range of computing tasks. This work showcases the potential for such processors to be used in diverse applications, from embedded systems and IoT devices to more complex computing environments, thereby illustrating the versatility and effectiveness of the proposed CPU design.