MRFIR: Area and power efficient modified reconfigurable FIR filter
Addanki Lakshmi Praharsha, Shaik Mohammad Irfan, Koppolu Srinivas, Gundugonti Kishore Kumar, Chinnapurapu Naga Raghuram · 2025
FIR filters hold a prominent role in digital signal processing (DSP). The FIR filter consists of numerous arithmetic operations like additions and multiplications. As multipliers consume substantial power and area, this paper proposes a modified multiplier that consumes less power and area. Using this modified multiplier, a novel FIR filter is proposed, which consumes less area and power compared to state-of-the-art works. The proposed FIR filter is implemented using Verilog HDL and synthesized with the Cadence Genus synthesis tool using 90nm technology. The proposed FIR filter achieves a 10.26% reduction in power for a 32-tap filter and a 16.99% reduction for a 64-tap filter. Additionally, it achieves a 7.96% reduction in area for a 32-tap filter and a 9.89% reduction for a 64-tap filter when compared to recently published research.