ECC Design for High-Speed Multi-Port Shared Cache Management Module
Panyu Chen, Yaxin Wang, Zhihao Liu, Huan Zhang, Fangjuan Wang · 2024
Aiming at the problem that data transmission errors are easy to occur in the data transmission process of cache scenarios, this paper designs an ECC processing module applied to high-speed multi-port shared cache, which effectively improves the ability of data error detection and timely error correction, and ensures the accuracy of high-speed data transmission. The ECC module includes Encoder and Decoder, and the algorithm is implemented by FPGA. When the data is input into the cache module, it is first encoded by Encoder, and the encoded data is stored in the cache module. When the data needs to be read from the cache module, the data will be decoded by the Decoder to restore the original valid data and detect whether there are errors in the data stream. Finally, the system can achieve one-bit, two-bit error detection, and can achieve one-bit error correction to achieve the reliability of data storage.