7-Stage Pipelined Architecture of ASCON for Resource Constraint Devices
A. J. Bhuvaneshwari, P. Kaythry, K. J. Jegadish Kumar, D. Sachin · IEEE Embedded Systems Letters · 2025
Ascon is an intended lightweight algorithm designed to deliver efficiency and security for resource-constrained Internet of Things (IoT) devices. This letter presents a field-programmable gate array (FPGA) implementation of the pipelined architecture of Ascon for rapid execution. The objective is to optimize the datapath to achieve high throughput while maintaining a minimal hardware footprint. The proposed 7-stage pipelined Ascon (7S-PASCON) algorithm enhances data processing, security, and performance. 7S-PASCON’s power efficiency is 2.5 times higher, throughput is 7 times higher, and latency is reduced to 31% for 100-MHz frequency than the standard Ascon. The proposed S-Box implementation uses a unified equation structure and reduces area usage by minimizing gate count and hardware resources. It has efficient resource utilization with a lookup table (LUT) efficiency of 14.39% and a flip-flop (FF) efficiency of 5.53% significantly better than existing works. The results demonstrate a tradeoff between resource utilization and potential performance enhancements compared to the nonpipelined version. The 7S-PASCON is beneficial for secure communication in IoT networks, wireless sensor networks, and defense systems.