Detection and Elimination of Single and Multiple Missing Gate Fault (SMGF/MMGF) of Reversible Arithmetic Circuits
Arindam Banerjee · 2025
In this paper, SMGF and MMGF detection and elimination technique for reversible arithmetic circuits have been reported. As arithmetic circuits, the author has considered only adder, subtractor, and adder–subtractor circuits. At first, faults are detected based on the optimized test patterns, and then circuit duplication technique has been used to eliminate the faults. An algorithm with low computational complexity has been created to generate the test patterns of the above-mentioned reversible arithmetic circuits. For the elimination of the fault, few extra gates are required, which make the circuit fault-free at the cost of the increment of ancillary input count, garbage output count, and quantum cost. The design is completely new, and there is no such literature available to the best of the knowledge of the author to compare the technique.